`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:09:12 04/09/2014 
// Design Name: 
// Module Name:    SBoxCipher 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module SBoxCipher(
	clk,
	rs232_rx,
	rs232_tx,
	rst,
	enc_dec
);

	input wire clk;
	input wire rs232_rx;
	output wire rs232_tx;
	input wire rst;
	input wire enc_dec;		// 0 for encrypt, 1 for decrypt
	
	wire [7:0] rx_buffer;
	wire [7:0] tx_buffer;
	wire [127:0] enc_icn_in;
	wire [127:0] enc_icn_out;
	wire [127:0] dec_vig_in;
	wire [127:0] dec_vig_out;
	wire [127:0] key;
	wire [127:0] data_in;
	wire [127:0] data_out;
	wire write_buffer;
	wire read_buffer;
	wire tx_full;
	wire rx_data_present;
	
	assign data_out = (enc_dec) ? dec_vig_out : enc_icn_out;

	uarts uart(
		.clk(clk),
		.rst(rst),
		.rs232_tx(rs232_tx),
		.rs232_rx(rs232_rx),
		.tx_buffer(tx_buffer),
		.rx_buffer(rx_buffer),
		.write_buffer(write_buffer),
		.read_buffer(read_buffer),
		.tx_full(tx_full),
		.rx_data_present(rx_data_present)
	);
	
	controller controlla(
		.rx_buffer(rx_buffer),
		.tx_buffer(tx_buffer),
		.data_present(rx_data_present),
		.buffer_full(tx_full),
		.read_strobe(read_buffer),
		.write_strobe(write_buffer),
		.data_in(data_out),
		.data_out(data_in),
		.key(key),
		.clk(clk)
	);
	
	Vigenere_enc vig_enc(
		.key(key),
		.data_in(data_in),
		.data_out(enc_icn_in),
		.clk(clk)
	);
	
	Omega_3x8_enc ICN_enc(
		.data_in(enc_icn_in),
		.data_out(enc_icn_out),
		.sel(key[23:0])
	);
	
	Vigenere_dec vig_dec(
		.key(key),
		.data_in(dec_vig_in),
		.data_out(dec_vig_out),
		.clk(clk)
	);
		
	Omega_3x8_dec ICN_dec(
		.data_in(dec_vig_in),
		.data_out(data_in),
		.sel(key[23:0])
	);
	
endmodule
